Chemical vapor deposition processes can form high quality layers or films on a semiconductor substrate or on an intermediate layer. Such a film can be an oxide film or thin oxide film, a silicon nitride passivation layer or etch stop layer, or a isolation trench fill layer. Such films tend to form at a relatively slow rate. However, there are two chemical vapor deposition processes capable of depositing films at relatively high rates, namely a plasma enhanced chemical vapor deposition (PECVD) process and a high density plasma chemical vapor deposition (HDPCVD) process. The PECVD process achieves high deposition rates by operating at a relatively high chamber pressure, on the order of about 1.5 Torr, to produce a dense process gas over the semiconductor wafer. The HDPCVD process achieves high deposition rates by generating a high density plasma. Both of these process may not be unsuitable for CVD processes for certain emerging integrated circuit technologies, specifically for the 65 nanometer technology at which features sizes are on the order of nanometers.
The PECVD process is unsuitable for fabricating 65 nanometer devices because the high chamber pressure employed by this process to boost the CVD deposition rate produces a high ion recombination rate, so that the plasma ion density is relatively small (about 10−5 ions/cc). Such a small plasma ion density reduces the contribution to the CVD chemical reaction energy of plasma ion collisions at the wafer surface. Therefore, the required CVD reaction energy can only be attained by heating the wafer to a relatively high temperature to supply the required chemical energy thermodynamically. Furthermore, the high chamber pressure results in such a high CVD deposition rate that the deposited film has a flake-like structure unless the wafer is heated to about 400° C. This has the effect of annealing out the flake-like imperfection in the crystal growth during deposition. Thus, a relatively high wafer temperature is required in the PECVD process in order to grow or deposit a high quality film. A problem arises in using such a PECVD process to fabricate 65 nm wafers. The 400° C. wafer temperature distorts the fine features by thermal diffusion or migration of dopants and other features in the wafer, so that the 65 nm features are distorted or destroyed. For example, the critical source-to-drain channel length between doped P-conductivity or N-conductivity regions may be reduced below a critical threshold at which device failure occurs. The magnitude of such feature distortion by thermal diffusion corresponds to the diffusion length, which is defined asD=k[t·T]1/2,where D is the mean distance over which atoms diffuse at a given temperature for a given duration, t is the duration or time during which the wafer is heated and T is the temperature to which the wafer is heated. At the temperature required to deposit a high quality layer in the PECVD process, dopants and other features diffuse beyond the 65 nm critical distance within the time required to perform the process. Reducing the wafer temperature to avoid diffusion beyond the 65 nm critical distance results in an unacceptably poor film quality. Therefore, the PECVD process employing a high chamber pressure is unsuitable for depositing high quality films on 65 nm devices.
The HDPCVD process takes the opposite approach by employing a very low chamber pressure (1.5 mTorr) to achieve a very high plasma ion density (10−1 ions/cc). The high plasma ion density results in a high plasma ion flux at the wafer surface that provides the needed chemical energy for the growth reaction, thereby promoting the growth process to realize a high growth rate. The HDPCVD process employs a low frequency inductively coupled plasma source that produces a very high plasma ion density with an ion generation region very close to the wafer surface. Such an inductively coupled reactor operated at such a low chamber pressure and low frequency cannot strike or maintain plasma without the application of a relatively large amount of source power, namely about 2 kW (minimum) of source power. At this minimum power level, the minimum plasma ion density is very high. This creates a problem, in that the minimum plasma ion density produces excessive plasma-heating of the wafer, driving the wafer temperature to about 400° C. Since this occurs at the minimum source power of the reactor for plasma ignition or plasma maintenance, the wafer temperature in the HDPCVD reactor is necessarily too high for a 65 nm device.
Another disadvantage of the PECVD and HDPCVD processes is independent of the device feature size, and arises from the high wafer temperatures that are required in the PECVD process and are unavoidable in the HDPCVD process: photoresist masking cannot survive such processes because the high wafer temperatures exceed the temperature at which photoresist is destroyed or removed from the wafer. Therefore, these PECVD and HDPCVD processes can only be employed in process steps requiring no photoresist masking, which greatly limits the utility of chemical vapor deposition (CVD) processes generally.
The PECVD process typically employs a high chamber pressure (1.5 Torr). The PECVD reactor capacitively couples RF source power at an HF frequency (e.g., 13.56 MHz) at a moderate power level (e.g., 600 W) to achieve a relatively low plasma ion-to-neutral ratio (10−5) and applies RF bias power at an LF frequency (e.g., under 400 kHz) at a moderate power level (e.g., 2 kW) to achieve a bias or wafer sheath voltage of under 100V. A heater heats the wafer up to the required high temperature. The resulting CVD deposition rate is about 5000 Å/min.
The HDPCVD process typically employs an inductively coupled reactor, for which the low chamber pressure (1.5 mTorr) is suitable. The HDPCVD reactor applies RF source power at an LF frequency (e.g., 2 MHz) at a very high power level (e.g., 10 kW) to achieve a very high plasma ion-to-neutral ratio (10−1) and applies RF bias power at an HF frequency (e.g., 13.56 MHz) in a power range from 0 to 2 kW) to achieve a bias or wafer sheath voltage in a corresponding range of 0 to 300V. Plasma heating heats the wafer up to a high temperature due to the high plasma ion density. The resulting CVD deposition rate is about 5000 Å/min.
The foregoing requirements for small source power level in the PECVD process and large source power level in the HDPCVD process militate against large changes in these respective source power levels. This fixes the CVD layer conformality for each of these processes. This is because the conformality of deposited CVD layers is determined by the source power level. (Conformality in a CVD process is the ratio of sidewall deposition rate to horizontal surface deposition rate.) Therefore, PECVD and HDPCVD processes each have a fixed conformality characteristic that cannot be greatly modified without distorting the process. In particular, the HDPCVD process requires a very high (10 kW) source power level, which produces a highly conformal CVD layer. Any departure from this regime would require a reduction in source power, which would in turn reduce plasma ion density. This is not feasible because the HDPCVD process relies on a very high plasma ion density to furnish the required energy to carry out the CVD growth or deposition reaction. This forces a high degree of conformality in the HDPCVD-deposited layer which cannot be escaped. Thus, the conformality of layers deposited in an HDPCVD process is necessarily high. Likewise, the PEDVD process produces layers having a low conformality. However, this has not been generally regarded as a problem because such processes have not been viewed as vehicles for adjusting conformality between high conformality and non-conformality.
In pursuing the present invention described below, we desire a CVD process in which conformality can be varied from about 0.1 (non-conformal) to about 0.5 or more (conformal), so that different layers can be formed that are respectively, conformal and non-conformal, and in which the wafer is maintained at a low temperature (so that the process is useful in 65 nm device fabrication) without sacrificing layer quality and without undue loss of productivity.
Another problem with conventional CVD processes arises in the filling of high aspect-ratio openings such as deep or shallow isolation trenches. The problem is that sidewall deposition during a CVD process for filling such a trench pinches off the bottom of the trench before it is filled, leaving an impermissible void in the completed structure. To avoid such a problem, it has been necessary in conventional practice to employ a process having the highest degree of non-conformality (to minimize sidewall deposition). This practice, however, limits the processes that can be used for trench filling. It also places a premium on the ability of the process engineer to maintain a high degree of non-conformality in the trench-filling (CVD) process. Therefore, we desire a CVD process in which the filling of high aspect-ratio openings such as trenches does not necessarily require deposition of a non-conformal CVD layer.